1. Field of the Invention
The present invention relates to an integrated circuit having dielectric isolation regions, which switches at a high speed, and more particularly, an IC driver capable of driving output power devices operating with a high breakdown voltage or a high blocking voltage at the high speed. The present invention also relates to a power integrated circuit (referred to as "power IC" hereinafter) merging output power devices and driver/controller for driving/controlling the output power devices in a same semiconductor chip, the chip having dielectric isolation regions, the power IC operating with a high breakdown voltage or a high blocking voltage at the high speed.
2. Description of the Related Art
A semiconductor integrated circuit--using SOI structure where a supporting substrate 1, a buried insulation film (SOI oxide film) 12, and Si films 140, 147, 139, 138, 137 are stacked beginning from the bottom as shown in FIG. 1--is characterized by an easiness for accomplishing a high breakdown voltage or high blocking voltage performance. The SOI semiconductor integrated circuit has the further advantages of small parasitic capacitance of respective integrated elements and an excellent adaptability to the high speed operation. Moreover, if Si films 140, 147, 139, 138, and 137 are made thinner, the SOI structure can suppress the short channel effect of semiconductor devices such as MOSFET (MOS Field Effect Transistor) disposed in the Si film 147 or the like and adopt a finer and finer structure, accomplishing higher integration densities. Usually, the semiconductor integrated circuit having SOI structure is composed by dielectric isolation region of Si films 140, 147, 139, 138, 137 formed on the SOI oxide film 12 into a plurality of islands 140, 147, 139, 138, 137 by element isolation regions composed of a trench side wall oxide film 6 and a buried trench polycrystalline silicon 7. FIG. 1 shows a dielectrically isolated (referred as "DI" hereinafter) integrated circuit of BiCMOS structure wherein a pMOS transistor composed of p.sup.+ source region 141 and p.sup.+ drain region 142 is disposed in the island 147 of Si, an nMOS transistor composed of n.sup.+ source region 511 and n.sup.+ drain region 512 in the island 139 of Si and an npn bipolar transistor composed of n.sup.+ injector region 601, p base area 602 and n.sup.+ collector region 602 in the island 138 of Si. The nMOS transistor is disposed in a p well 501 and p.sup.+ contact region 512 is disposed in the p well 501. On the other hand, n.sup.+ contact region 143 is disposed in the island 147 of Si.
In the field of power semiconductor device (power device), a DI integrated circuit driver as shown in FIG. 2 is well known. In general, by such DI integrated circuit driver, an output power device unit external to the IC driver is driven. FIG. 2 shows a DI integrated circuit driver, called "half-bridge driver". Particularly when a high breakdown voltage or high blocking voltage is required for the output power device unit, the output power device unit is composed by serial connection of an upper-side output power device Q.sub.u1 and a lower-side output power device Q.sub.d1, and this output power device unit is driven by a half bridge driver, as shown in FIG. 2. In this case, one main electrode of the upper-side output power device Q.sub.u1 is connected to a positive high level power supply 101 while one main electrode of the lower-side output power device Q.sub.d1 to a ground potential (GND). The other main electrode of the upper-side output power device Q.sub.u1 and the other main electrode of the lower-side output power device Q.sub.d1 are connected to a neutral point terminal N.sub.n1, while this neutral point terminal N.sub.n1 is connected to a load not illustrated.
As shown in FIG. 2, the upper-side output power device Q.sub.u1 is driven by an upper-side driver 102 in "a floating state". In other words, an output terminal N.sub.u1 of the upper-side driver 102 of the IC driver is connected to the control electrode of the external upper-side output power device Q.sub.u1. On the other hand, an output terminal N.sub.d1 of the lower-side driver 103 of the IC driver is connected to the control electrode of the external lower-side output power device Q.sub.d1. The upper-side driver 102 is connected between an internal power supply circuit 105 and the neutral point terminal N.sub.n1 and supplied with an predetermined power supply voltage. On the other hand, the lower-side driver 103 is connected between a low level power supply 106 and the ground potential (GND) and supplied with an predetermined power supply voltage. An upper-side control signal from an distribution logic 104 is supplied to the upper-side driver 102 via a transistor Q.sub.c, while a lower-side control signal from the distribution logic 104 is supplied directly to the lower-side driver 103.
In the semiconductor integrated circuit having SOI structure, the upper-side driver 102, lower-side driver 103, distribution logic 104, internal power supply circuit 105 or the like are disposed respectively in a plurality of islands. In FIG. 2, an upper-side recovery diode D.sub.u1 is connected in parallel to the nMOSFET as upper-side output power device Q.sub.u1 and an lower-side recovery diode D.sub.d1 to the nMOSFET as lower-side output power device Q.sub.d1.
FIG. 3 also is a circuit diagram showing a similar conventional IC driver. Namely, it shows more in detail the upper-side driver 102 and the lower-side driver 103 composing an IC driver. The upper-side driver 102 is composed of an upper-side CMOS inverter 111, an upper-side buffer amp 121 and an upper-side control logic 131, while lower-side driver 103 is composed of a lower-side CMOS inverter 112, a lower-side buffer amp 122 and a lower-side control logic 132. FIG. 3 shows an example where an insulated gate bipolar transistor (IGBT) is used respectively as external upper-side output power device Q.sub.u2 and lower-side output power device Q.sub.d2. An upper-side recovery diode D.sub.u2 is connected in parallel to the upper-side output power device Q.sub.u2 and an lower-side recovery diode D.sub.d2 to the lower-side output power device Q.sub.d2.
In the circuit configuration shown in FIG. 2 and FIG. 3, the upper-side output power device Q.sub.u1, Q.sub.u2 and the lower-side output power device Q.sub.d1, Q.sub.d2 are driven by the upper-side driver 102 and the lower-side driver 103 and switched on and off alternatively. As the result, the potential of the neutral point terminal N.sub.n1, N.sub.n2 repeats increase and decrease between potential levels of the ground potential (GND) and the high level power supply 101 in accordance with the alternative on and off of the upper-side output power device Q.sub.u1, Q.sub.u2 and the lower-side output power device Q.sub.d1, Q.sub.d2.
FIG. 4 shows schematically the waveform of this switching state composed of these repeated increases and decreases. FIG. 4 illustrates only the operation of 3 cycles; however, it is obvious that such cycle is repeated for a predetermined period of time. Namely, FIG. 4 shows three outputs sections corresponding to an upper-side output O.sub.u at nodes N.sub.u1, N.sub.u2, a neutral output O.sub.n at node N.sub.n1, N.sub.n2 and a lower-side output O.sub.d at nodes N.sub.d1, N.sub.d2 of FIG. 2 and FIG. 3. Note that inflection points of respective waveforms overlap substantially each other, while the position on the X axis of respective outputs O.sub.u, O.sub.n, O.sub.d is slightly displaced in FIG. 4 for illustrative convenience. The upper-side output O.sub.u biases the gate of the external upper-side output power device Q.sub.u1, Q.sub.u2, while the lower-side output O.sub.d biases the gate of the lower-side output power device Q.sub.d1, Q.sub.d2. For the first 1/2 cycle, the lower-side output power device Q.sub.d supply a predetermined potential (gate bias) O.sub.d measured from the GND, while the upper-side output power device Q.sub.u is almost zero in respect of the neutral point output On. In the following 1/2 cycle, the output O.sub.d of the lower-side output power device Q.sub.d is almost GND, while the upper-side output power device Q.sub.u feeds the predetermined gate bias O.sub.u measured from the potential of the neutral output O.sub.n. As the gate bias is applied alternatively to the gate of upper and lower output power devices (power device) Q.sub.u1, Q.sub.u2 ; Q.sub.d1, Q.sub.d2 in respect of respective source potential, the upper-side output power device Q.sub.u1, Q.sub.u2 and the lower-side output power device Q.sub.d1, Q.sub.d2 are turned on and off alternatively. The neutral point output O.sub.n swings between the high level power supply V.sub.pp and GND accordingly.
As shown in FIG. 2 and FIG. 3, the lowest potential of the lower-side driver 103 and the lowest potential of the distribution logic 104 are both fixed to GND. However, the lowest potential of the upper-side driver 102 swings as it increases and decreases in accordance with the variation of the neutral point N.sub.n1, N.sub.n2.
FIG. 5A is a circuit diagram showing only the proximity of the CMOS inverter composing the upper-side driver 102 of FIG. 3. As shown in FIG. 5A, the CMOS inverter is composed of a pMOS transistor Q.sub.p1 and an nMOS transistor Q.sub.n1, and its output is input in the gate of the IGBT as upper-side output power device Q.sub.u2. An upper-side recovery diode D.sub.u2 is connected in parallel to the upper-side output power device Q.sub.u2.
FIG. 5B is a plane diagram representing this CMOS inverter 111, in which the upper-side output power device Q.sub.u2 and the upper-side recovery diode D.sub.u2 shown in FIG. A are not illustrated. As shown in FIG. 5B, the pMOS transistor Q.sub.p1 is disposed in an n type semiconductor island 147 while the nMOS transistor Q.sub.n1 is disposed in a p type semiconductor island 157. Respective n type semiconductor island 147 and p type semiconductor island 157 are separated each other by an element isolation region composed of the trench side wall insulation film 6 and the buried trench polycrystalline silicon 7. As shown in FIG. 5B, the pMOS transistor Q.sub.p1 comprises at least a p.sup.+ source region 141, a p.sup.+ drain region 142, and an impurity doped polycrystalline silicon (called "doped polycrystalline silicon" hereinafter) gate electrode 144. On the other hand, the nMOS transistor Q.sub.n1 comprises at least an n.sup.+ source region 151, a n.sup.+ drain region 152, and a doped polycrystalline silicon gate electrode 154. Moreover, an n.sup.+ substrate contact region 143 is disposed in the n type semiconductor island 147, and the n.sup.+ substrate contact region 143 and the p.sup.+ source region 141 are connected each other, through a metallic wiring 145 from the internal power supply circuit 105. Similarly, a p.sup.+ substrate contact region 153 is disposed in the p type semiconductor island 157, and the p.sup.+ substrate contact region 153 and the n.sup.+ source region 151 are connected each other through a metallic wiring 155 of the neutral point (intermediate) potential. Doped polycrystalline silicon gate electrodes 144, 154 composing the CMOS inverter shown in FIG. 5B are connected to the upper-side buffer amp 121 (see FIG. 3) through a metallic wiring 161, and the drive signal is input to the doped polycrystalline silicon gate electrodes 144, 154 through this metallic wiring 161. Moreover, the p.sup.+ drain region 142 of the pMOS transistor Q.sub.p1 and the n.sup.+ drain region 152 of the nMOS transistor Q.sub.n1 are connected each other through a metallic wiring 162. This metallic wiring 162 is lead to the gate of the IGBT acting as upper-side output power device Q.sub.u2.
FIG. 5C is a cross-sectional view along the line V--V of FIG. 5B. Namely, FIG. 5C shows a SOI structure where an n type semiconductor island 147, semiconductor islands 148, 149 are formed on the supporting substrate 1 through the SOI oxide film (buried insulation film) 12. In this SOI structure, a MOS capacitor structure is composed where the SOI oxide film (buried insulation film) 12 constitutes the capacitor insulation film, the n type semiconductor island 147 the upper electrode and a back electrode 2 the lower electrode, forming a parasitic condenser C.sub.SUB. If the supporting substrate 1 has high resistivity and can be taken as a dielectric, the supporting substrate 1 functions as the capacitor insulation film, and if the supporting substrate 1 has so low resistivity that it can be taken substantially as a conductor, the supporting substrate 1 functions as the lower electrode.
Thus, provided with the parasitic condenser C.sub.SUB, in the SOI structure DI-IC driver (referred as "SOI DI-IC driver" hereinafter), if the neutral point output voltage variation rate dV/dt increases in switching speed more than several kV/.mu.sec, the displacement current J.sub.d in the parasitic condenser C.sub.SUB between the semiconductor island 147 arranging a switching device composing the upper-side driver 102 and the back electrode 2 increases. As the consequence, in an IC driver using as device forming area the n type semiconductor island 147 in floating state as shown in FIG. 6, the displacement current J.sub.d flows from the internal power supply circuit 105 to the bottom parasitic MOS (MIS) structure C.sub.SUB, through the p.sup.+ source region 141. Additionally, if the displacement current J.sub.d flows over the driving capability of the internal power supply circuit 105, the power supply voltage decreases, making the operation of the upper-side driver 102 unstable.
However, the switching speed (voltage variation rate) for such half bridge circuit requires in general approximately 20 kV/.mu.sec, and the conventional IC driver requiring a voltage variation rate equal or superior to about 20 kV/.mu.sec will require an excessive current handling capability of the internal power supply circuit, in order to assure a stable operation of the upper-side driver 102.
Thus, in the conventional SOI DI-IC driver, if the high speed operation increases the displacement current J.sub.d, to increase the current load of the internal power supply circuit 105 excessively, over the driving capability of the current limit device composing the internal power supply circuit 105, the output voltage happens to decrease. Or, even then the driving capability is not exceeded, a sudden load variation will cause a time lag to feedback this situation, provoking a lower output voltage with this time lag. Therefore, the internal power supply circuit 105 should be made more complex and larger so as to insure higher current handling capability, in order to prevent such output voltage drop. Therefore, the internal power supply circuit 105 will occupy more space, inhibiting minimize of the IC driver chip size. Moreover, a larger internal power supply circuit 105 increases the power dissipation of the driving circuit, lowering the total power conversion efficiency of the system.
Though a pMOS transistor is illustrated in FIG. 6, such problem is not limited to the pMOS transistor. Even in an nMOS transistor, npn bipolar transistor, pnp bipolar transistor, or other semiconductor devices such as diode, such problem may happen in a DI integrated circuit of the structure having a p diffusion layer or n diffusion layer forming the semiconductor island presenting the floating state and where this p diffusion layer or n diffusion layer is connected to the internal power supply circuit or other circuit than the internal power supply circuit. For example, a similar problem may happen in a case where a p well exists in an n type semiconductor island and an nMOS transistor is formed therein. In many IC drivers, the p well in the n type semiconductor island is connected to the low potential side, or to the reference potential (neutral point potential). This case will not present the floating state and the problem may not be significant. However, in the nMOS transistor where the p well is used in floating state, namely lifted from the reference potential, the displacement current J.sub.d flows in the bottom parasitic MOS (MIS) structure, and the extra current of the internal power supply circuit increases excessively, to lower the output voltage of the internal power supply circuit disadvantageously or to affect the other circuit than the internal power supply circuit to fluctuate the circuit parameters and circuit operation detrimentally.
If we suppose a power IC in which Zener diodes ZD.sub.u and ZD.sub.d are connected between the gate and source electrodes of the respective upper-side output power device Q.sub.u1 and lower-side output power device Q.sub.d1 as shown by broken lines in FIG. 2, the electron current flows from cathode to anode direction of the Zener diode ZD.sub.u for compensating the displacement current J.sub.d in the bottom of parasitic MOS (MIS) structure, thereby causing a sudden drop of the gate potential of the upper-side output power device Q.sub.u1, resulting in an undesired malfunction of the system. Then electrons can be injected from the n diffused layer, causing similar disadvantage as the case for the p diffused layer. Instead of the gate of the upper-side output power device Q.sub.u1, if the n diffused layer is connected to a specific circuitry, the electrons injected from the n diffused layer for compensating the displacement current J.sub.d in the bottom of parasitic MOS (MIS) structure affect the specific circuitry so as to fluctuate the circuit parameters.
Therefore, the displacement current J.sub.d in the bottom of parasitic MOS (MIS) structure becomes significant in various situations and various structures irrespective of p or n diffused layer, to make circuit parameters of the DI integrated circuit seriously changeable and unreliable.